The present invention relates to semiconductor manufacturing technology, and, more specifically, to the analysis and determination of potential process driven test fails during very large scale integrated circuit (VLSI) chip testing and to finding common test fail signatures when running different test patterns indicating potential redundant test patterns.
Process related chip test issues are difficult to identify and map to test fails at the chip tester by the test engineer who normally is not a process engineer. Identified dependencies between test fails and process fails allow one to determine whether chip test fails are somehow related to process fails coming from production. Especially in the design phase of VLSI chip components, it is more often the case that circuit designs are used in test chips or intermittent design levels of product chips without having final product quality. When such a chip is tested in a fabric test environment, some test fails can happen. These fails can have multiple root causes, but mainly there exist two aspects: either design sensitivities against certain valid process parameters or process tolerances leaving or outside of valid ranges.
In addition, test patterns may be optimized against a test model representing the chip or device under test. Optimization targets for test patterns may include test time, test volume (i.e., size), test coverage, etc. It is known to find redundant test patterns to reduce test time and test data volume without reducing test coverage. However, there are process variations in the chip fabric that are not necessarily fed back or reflected in the test model for the device or design under test. This leads to slightly changing test fail signatures over time and over the wide process range or tolerances for such a device under test. Understanding common fail signatures when running different test patterns can indicate potential redundant tests.